1. Field of the Invention
This invention relates to a high speed interconnect network for a cluster of processors and, more particularly, for such a network which is adapted to interconnect a number of concurrently active microprocessors via a common system backplane bus.
2. Description of the Prior Art
With the advent of multiprocessing, processors normally dealt with one or more main memories through some sort of crosspoint exchange such as is disclosed in the Lynch et al U.S. Pat. Nos. 3,302,182 and 3,411,139. However, the processors did not directly communicate with each other. Furthermore, such a crosspoint exchange was expensive to manufacture since it was only employed in large computer systems having relatively large data transfer rates.
Most of the early work done in networking was more concerned with coupling peripheral devices such as terminals to the main memory by way of an I/O controller. Usually, data transfer from the peripheral devices to the I/O controller was in a serial-by-bit manner although in certain situations serial-by-byte transfers were employed. However, all transfers were under control of the I/O controller and the peripheral devices or terminals did not communicate with one another. A more recent example of such serial connection of terminals to a controller is illustrated in the Seitz et al U.S. Pat. No. 4,156,277.
In more recent times, networks for terminals have been developed without requiring a controller for data transfer between the terminals which have their own controllers in the form of microprocessors. However, such networks employed serial data transfers due to the relatively low switching speeds of the individual microprocessors. An example of such a local area network is illustrated in the Malcolm et al U.S. patent application Ser. No. 145,606, filed May 1, 1980 and assigned to the assignee of the present invention.
Such networks were designed for terminals each of which was provided with its own control processor and it was recognized that networks of processors per se could be created for concurrent processing with processors communicating with one another and usually being provided with their own memories for storage. Networks of such concurrent processors are illustrated in the Barton et al U.S. Pat. No. 4,307,446, and in the Hagenmaier et al U.S. patent application, Ser. No. 281,065 filed July 7, 1981 and assigned to the assignee of the present invention. However, in both of these references data transfer was still serial-by-bit because of the low transfer rate required between the individual processors which were still microprocessors embodied in individual integrated circuit chips or else on a wafer containing a number of such integrated dies. Furthermore, information transfer was by way of packets of information and, once a processor had access to a channel or bus, other processors could not transmit without causing collisions and loss of information.
It has now been recognized that a large number of such processors can be coupled together to control, for example, large data comm networks. However, because of the demands of such networks, it is desirable to increase the throughput of the overall processor network which requires a relatively high speed cross connection even though the transfer rates of individual procssors is relatively small.
It is then an object of the present invention to provide a high speed network for transfer of information between processors that are concurrently active.
A further object of the present invention is to provide a high speed network between processors that have characteristically lower speeds than that of the network without slowing down the network to the characteristic speeds of the processors.
Another object of the present invention is to provide such a high speed network for a relatively large number of processors which may be microprocessors that are coupled across a common backplane by the network.
It is still another object of the present invention to provide a network for a relatively large number of processors that can be expanded to accommodate even greater numbers of processors.